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| 19-4932; 11/09 DS2482-800 Eight-Channel 1-Wire Master www.maxim-ic.com The DS2482-800 is an IC to 1-Wire bridge device that interfaces directly to standard (100kHz max) or fast (400kHz max) IC masters to perform bidirectional protocol conversion between the IC master and any downstream 1-Wire slave devices. Relative to any attached 1-Wire slave device, the DS2482-800 is a 1-Wire master. Internal factorytrimmed timers relieve the system host processor from generating time-critical 1-Wire waveforms, supporting both standard and Overdrive 1-Wire communication speeds. To optimize 1-Wire waveform generation, the DS2482-800 performs slew-rate control on rising and falling 1-Wire edges and has a programmable feature to mask the fast presence pulse edge that some 1-Wire slave devices can generate. Programmable strong pullup features support 1-Wire power delivery to 1-Wire devices such as EEPROMs and sensors. The DS2482-800 combines these features with eight independent 1Wire I/O channels. The IC slave address assignment is controlled by three binary address inputs, resolving potential conflicts with other IC slave devices in the system. GENERAL DESCRIPTION FEATURES IC Host Interface, Supports 100kHz and 400kHz IC Communication Speeds 1-Wire Master I/O with Selectable Active or Passive 1-Wire Pullup Provides Reset/Presence, 8-Bit, Single-Bit, and Three-Bit 1-Wire I/O Sequences Eight Channels of Independently Operated 1-Wire I/O Standard and Overdrive 1-Wire Communication Speeds Slew Controlled 1-Wire Edges Supports Low-Impedance 1-Wire Strong Pullup for EEPROMs, Temp Sensors, or Other 1-Wire Slaves That Have Momentary High Current Modes Three Address Inputs for IC Address Assignment Wide Operating Range: 2.9V to 5.5V, -40C to +85C 16-Pin SO Package (150 mil) PART DS2482S-800+ DS2482S-800+T&R TEMP RANGE -40 to +85C -40 to +85C PIN-PACKAGE 16 SO (150 mil ) 16 SO (150 mil ) ORDERING INFORMATION APPLICATIONS Wireless Base Stations Central Office Switches PBXs Rack-Based Servers Medical Clinical Diagnostic Equipment +Denotes a lead(Pb)-free/RoHS-compliant package. T&R = Tape and reel. PIN CONFIGURATION IO3 SCL SDA VCC NC AD2 AD1 AD0 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 IO2 IO1 IO0 GND IO4 IO5 IO6 IO7 TYPICAL OPERATING CIRCUIT 1-Wire is a registered trademark of Maxim Integrated Products, Inc. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 23 DS2482-800: Eight-Channel 1-Wire Master ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground Maximum Current Into Any Pin Operating Temperature Range Junction Temperature Storage Temperature Range Soldering Temperature -0.5V, +6V 20mA -40C to +85C +150C -55C to +125C See IPC/JEDEC J-STD-020A Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device. ELECTRICAL CHARACTERISTICS (VCC = 2.9V to 5.5V, TA = -40C to +85C.) PARAMETER Supply Voltage Operating Current 1-Wire Input High 1-Wire Input Low 1-Wire Weak Pullup Resistor 1-Wire Output Low Active Pullup On Time Strong Pullup Voltage Drop 3.3V Pulldown Slew Rate (Note 6) 5V Pulldown Slew Rate (Note 6) 3.3V Pullup Slew Rate (Note 6) 5V Pullup Slew Rate (Note 6) Power-On Reset Trip Point SYMBOL VCC ICC VIH1 VIL1 RWPU VOL1 tAPUOT VSTRPU CONDITIONS 3.3V 5V (Note 1) 3.3V (Notes 2, 3) 5V (Notes 2, 3) 3.3V (Notes 2, 3) 5V (Notes 2, 3) (Note 4) At 4mA load Standard (Notes 4, 16) Overdrive (Notes 4, 16) VCC 3.2V, 1.5mA load VCC 5.2 V, 3mA load Standard (3.3V 10%) Overdrive (3.3V 10%) Standard (5.0V 10%) Overdrive (5.0V 10%) Standard (3.3V 10%) Overdrive (3.3V 10%) Standard (5.0V 10%) Overdrive (5.0V 10%) MIN 2.9 4.5 1.9 3.4 TYP 3.3 5.0 MAX 3.7 5.5 0.75 UNITS V mA V 0.75 1.0 800 2.3 0.4 2.5 0.5 1675 0.4 2.7 0.6 0.3 0.5 1 5 2 10 0.8 2.7 1.3 3.4 4.2 22.1 6.5 40 4 20 6 31 2.2 V V s V V/s V/s V/s V/s V PDSRC PDSRC PUSRC PUSRC VPOR 1-Wire TIMING (Note 15) See Figures 4, 5, and 6 Write 1/Read Low Time Read Sample Time 1-Wire Time Slot Fall Time High-to-Low at Standard Speed (Note 6) Fall Time High-to-Low at Overdrive Speed (Note 6) tW1L tMSR tslot Standard Overdrive Standard Overdrive Standard Overdrive 3.3V to 0V (Note 5) 5.0V to 0V (Note 5) 3.3V to 0V (Note 5) 5.0V to 0V (Note 5) 2 of 23 7.6 0.9 13.3 1.4 65.8 9.9 0.54 0.55 0.10 0.09 8 1 14 1.5 69.3 10.5 8.4 1.1 15 1.8 72.8 11.0 3.0 2.2 0.59 0.44 s s s tF1 s DS2482-800: Eight-Channel 1-Wire Master PARAMETER Write 0 Low Time Write 0 Recovery Time Reset Low Time Presence-Detect Sample Time Sampling for Short and Interrupt Reset High Time IC-Pins (Note 7) See Figure 9 LOW Level Input Voltage HIGH Level Input Voltage Hysteresis of Schmitt Trigger Inputs LOW Level Output Voltage at 3mA Sink Current Output Fall Time from VIhmin to VILmax with a Bus Capacitance from 10pF to 400pF Pulse Width of Spikes that are Suppressed by the Input Filter Input Current Each I/O Pin with an Input Voltage Between 0.1VCCmax and 0.9VCCmax Input Capacitance SCL Clock Frequency Hold Time (Repeated) START Condition. After this Period, the First Clock Pulse is Generated. LOW Period of the SCL Clock HIGH Period of the SCL Clock Setup Time for a Repeated START Condition Data Hold Time Data Setup Time Setup Time for STOP Condition Bus Free Time Between a STOP and START Condition Capacitive Load for Each Bus Line Oscillator Warm-Up Time SYMBOL tW0L tREC0 tRSTL tMSP tSI tRSTH CONDITIONS Standard Overdrive Standard Overdrive Standard Overdrive Standard Overdrive Standard Overdrive Standard Overdrive MIN 60 7.1 5.0 2.8 570 68.4 66.5 7.1 7.6 0.7 554.8 70.3 TYP 64 7.5 5.3 3.0 600 72 70 7.5 8 0.75 584 74 MAX 68 7.9 5.6 3.2 630 75.6 73.5 7.9 8.4 0.8 613.2 77.7 0.25 x VCC 0.22 x VCC VCC + 0.5V UNITS s s s s s s VIL VIH Vhys VOL tof tSP Ii Ci fSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tSU:STO tBUF Cb tOSCWUP VCC = 2.9V to 3.7V VCC = 4.5V to 5.5V -0.5 0.7 x VCC 0.05 x VCC V V V 0.4 60 SDA and SCL pins only (Notes 8, 9) (Note 8) 0 0.6 1.3 0.6 0.6 (Notes 10, 11) (Note 12) 0.9 250 0.6 1.3 (Note 13) (Note 14) 400 100 -10 250 50 10 10 400 V ns ns A pF kHz s s s s s ns s s pF s 3 of 23 DS2482-800: Eight-Channel 1-Wire Master Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Operating current with 1-Wire write byte sequence followed by continuous Read of Status Register at 400KHz in Overdrive. With standard speed the total capacitive load of the 1-Wire bus should not exceed 1nF, otherwise the passive pullup on threshold VIL1 may not be reached in the available time. With Overdrive speed the capacitive load on the 1-Wire bus must not exceed 300pF. Active pullup guaranteed to turn on between VIL1MAX and VIH1MIN. Active or resistive pullup choice is configurable. Fall time high to low (tF1) is derived from PDSRC, referenced from 0.9 x VCC to 0.1 x VCC. These values apply at full load, i. e., 1nF at standard speed and 0.3nF at Overdrive speed. For reduced load, the pulldown slew rate is slightly faster. All IC timing values are referred to VIHmin and VILmax levels. Applies to SDA, SCL, and AD0, AD1, AD2. I/O pins of the DS2482 do not obstruct the SDA and SCL lines if VCC is switched off. The DS2482 provides a hold time of at least 300ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. A Fast-mode IC-bus device can be used in a standard-mode IC-bus system, but the requirement tSU:DAT 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tSU:DAT = 1000 + 250 = 1250ns (according to the standard-mode IC-bus specification) before the SCL line is released. CB = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times according to IC-Bus Specification v2.1 are allowed. IC communication should not take place for the max tOSCWUP time following a power-on reset. Except for tF1, all 1-Wire timing specifications and tAPUOT are derived from the same timing circuit. Therefore, if one of these parameters is found to be off the typical value, it is safe to assume that all of these parameters deviate from their typical value in the same direction and by the same degree. Note 13: Note 14: Note 15: PIN DESCRIPTION PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NAME IO3 SCL SDA VCC NC AD2 AD1 AD0 IO7 IO6 IO5 IO4 GND IO0 IO1 IO2 FUNCTION IO Driver for 1-Wire Line #3 IC Serial Clock Input; must be tied to VCC through a pullup resistor. IC Serial Data Input/Output; must be tied to VCC through a pullup resistor. Power Supply Input Not Connected IC Address Inputs; must be tied to VCC or GND. These inputs determine the IC slave address of the device, see Figure 8. IO Driver for 1-Wire Line #7 IO Driver for 1-Wire Line #6 IO Driver for 1-Wire Line #5 IO Driver for 1-Wire Line #4 Ground Reference IO Driver for 1-Wire Line #0 IO Driver for 1-Wire Line #1 IO Driver for 1-Wire Line #2 4 of 23 DS2482-800: Eight-Channel 1-Wire Master Figure 1. Block Diagram Line XCVR T-Time OSC Line XCVR Line XCVR Line XCVR Line XCVR Line XCVR Line XCVR Line XCVR IO0 IO1 Config Register IO2 I/O Controller Channel Select IO3 SDA SCL IC Interface Controller Status Register Read Data Register IO4 AD0 AD1 AD2 IO5 IO6 IO7 DETAILED DESCRIPTION The DS2482-800 is a self-timed 8-channel 1-Wire master, which supports advanced 1-Wire waveform features including standard and Overdrive speeds, active pullup, and strong pullup for power delivery. Once supplied with command and data, the I/O controller of the DS2482 performs time-critical 1-Wire communication functions such as reset/presence detect cycle, read-byte, write-byte, single-bit R/W and triplet for ROM Search, without requiring interaction with the host processor. The host obtains feedback (completion of a 1-Wire function, presence pulse, 1Wire short, search direction taken) through the Status Register and data through the Read Data register. The DS2482 communicates with a host processor through its IC bus interface in standard-mode or in fast-mode. The logic state of three address pins (2 address pins with the 1-channel version) determines the IC slave address of the DS2482, allowing up to 8 devices operating on the same bus segment without requiring a hub. DEVICE REGISTERS The DS2482 has four registers that the IC host can read: Channel Selection, Configuration, Status, and Read Data. These registers are addressed by a read pointer. The position of the read pointer, i.e., the register that the host will read in a subsequent read access, is defined by the instruction that the has DS2482 executed last. The host has read and write access to the Channel Selection and Configuration Registers to select one of several 1Wire channels and to enable certain 1-Wire features. 5 of 23 DS2482-800: Eight-Channel 1-Wire Master Channel Selection Register The content of the Channel Selection Register specifies which of the channels is selected and will be the target of subsequent 1-Wire communication commands. The DS2482-800 supports eight 1-Wire communication channels IO0 to IO7. Only one of these channels can be active/selected at any time. Once selected, a 1-Wire channel remains selected until a different channel is selected through the Channel Select command or by initiating a device reset. After a device reset (power-up cycle or initiated by the Device Reset command) the IO0 channel is selected. Configuration Register The DS2482 supports allows three 1-Wire features that are enabled or selected through the Configuration Register. These features are: Active Pullup (APU) Strong Pullup (SPU) 1-Wire Speed (1WS) These features can be selected in any combination. They apply equally to all 1-Wire channels. While APU, PPM and 1WS maintain their state, SPU returns to its inactive state as soon as the strong pullup has ended. Configuration Register Bit Assignment bit 7 1WS bit 6 SPU bit 5 1 bit 4 APU bit 3 1WS bit 2 SPU bit 1 0 bit 0 APU After a device reset (power-up cycle or initiated by the Device Reset command) the Configuration Register reads 00h. When writing to the Configuration Register, the new data is accepted only if the upper nibble (bits 7 to 4) is the one's complement of the lower nibble (bits 3 to 0). When read, the upper nibble is always 0h. Active Pullup (APU) The APU bit controls whether an active pullup (controlled slew-rate transistor) or a passive pullup (RWPU resistor) will be used to drive a 1-Wire line from low to high. When APU = 0, active pullup is disabled (resistor mode). Active Pullup should always be selected unless there is only a single slave on the 1-Wire line. The active pullup does not apply to the rising edge of a presence pulse or a recovery after a short on the 1-Wire line. The circuit that controls rising edges (Figure 2) operates as follows: At t1 the pulldown (from DS2482 or 1-Wire slave) ends. From this point on the 1-Wire bus is pulled high through RWPU internal to the DS2482. VCC and the capacitive load of the 1-Wire line determine the slope. In case that active pullup is disabled (APU = 0), the resistive pullup continues, as represented by the solid line. With active pullup enabled (APU = 1), when at t2 the voltage has reached a level between VIL1max and VIH1min, the DS2482 actively pulls the 1-Wire line high applying a controlled slew rate, as represented by the dashed line. The active pullup continues until tAPUOT is expired at t3. From that time on the resistive pullup will continue. Figure 2. Rising Edge Pullup VCC VIH1MIN APU = 1 APU = 0 VIL1MAX 0V 1-Wire bus is discharged tAPUOT t1 t2 t3 6 of 23 DS2482-800: Eight-Channel 1-Wire Master Strong Pullup (SPU) The SPU bit controls whether the DS2482 applies a low-impedance pullup to VCC on the 1-Wire line after the last bit of either a 1-Wire Write Byte command or after a 1-Wire Single Bit command has completed. The strong pullup feature is commonly used with 1-Wire EEPROM devices when copying scratchpad data to the main memory or when performing a SHA-1 computation, and with parasitically powered temperature sensors or A-to-D converters. The respective device data sheets specify the location in the communications protocol after which the strong pullup should be applied. The SPU bit in the configuration register of the DS2482 must be set immediately prior to issuing the command that puts the 1-Wire device into the state where it needs the extra power. If SPU is 1, the DS2482 applies active pullup to the rising edge of the time slot in which the strong pullup starts, regardless of the APU bit setting. However, in contrast to setting APU = 1 for active pullup, the low-impedance pullup will not end after tAPUOT is expired. Instead, as shown in Figure 3, the low-impedance pullup remains active until: a) the next 1-Wire communication command (the typical case), b) by writing to the Configuration Register with the SPU bit being 0 (alternative), or c) by issuing the Device Reset command. Additionally, when the pullup ends, the SPU bit is automatically reset to 0. Using the strong pullup does not change the state of the APU bit in the Configuration Register. Figure 3. Low-Impedance Pullup Timing Vcc Last bit of 1-Wire Write Byte or 1-Wire Single Bit Function Write 1 Edges with active pull-up Write 0 0V tSLOT Pull-up DS2482 Pull-down Next Time Slot DS2482 Low Impedance Pull-up 7 of 23 DS2482-800: Eight-Channel 1-Wire Master 1-Wire Speed (1WS) The 1WS bit determines the timing of any 1-Wire communication generated by the DS2482. All 1-Wire slave devices support standard speed (1WS = 0), where the transfer of a single bit (tSLOT in Figure 3) is completed within 65s. Many 1-Wire device can also communicate at a higher data rate, called Overdrive speed. To change from standard to Overdrive speed, a 1-Wire device needs to receive an Overdrive Skip ROM or Overdrive Match ROM command, as explained in the device data sheets. The change in speed occurs immediately after the 1-Wire device has received the speed-changing command code. The DS2482 must take part in this speed change to stay synchronized. This is accomplished by writing to the Configuration Register with the 1WS bit being 1 immediately after the 1-Wire Byte command that changes the speed of a 1-Wire device. Writing to the Configuration Register with the 1WS bit being 0 followed by a 1-Wire Reset command changes the DS2482 and any 1-Wire devices on the active 1-Wire line back to standard speed. Status Register The read-only Status Register is the general means for the DS2482 to report bit-type data from the 1-Wire side, 1Wire busy status and its own reset status to the host processor. All 1-Wire communication commands and the Device Reset command position the read pointer at the Status Register for the host processor to read with minimal protocol overhead. Status information is updated during the execution of certain commands only. Details are given in the description of the various status bits below. Status Register Bit Assignment bit 7 DIR bit 6 TSB bit 5 SBR bit 4 RST bit 3 LL bit 2 SD bit 1 PPD bit 0 1WB 1-Wire Busy (1WB) The 1WB bit reports to the host processor whether the 1-Wire line is busy. During 1-Wire communication 1WB is 1; once the command is completed, 1WB returns to its default 0. Details on when 1WB changes state and for how long it remains at 1 are found in the Function Commands section. Presence Pulse Detect (PPD) The PPD bit is updated with every 1-Wire Reset command. If the DS2482 detects a presence pulse from a 1-Wire device at tMSP during the Presence Detect cycle, the PPD bit will be set to 1. This bit will return to its default 0 if there is no presence pulse or if the 1-Wire line is shorted during a subsequent 1-Wire Reset command. Short Detected (SD) The SD bit is updated with every 1-Wire Reset command. If the DS2482 detects a logic 0 on the 1-Wire line at tSI during the Presence Detect cycle, the SD bit will be set to 1. This bit will return to its default 0 with a subsequent 1Wire Reset command provided that the short has been removed. If SD is 1, PPD will be 0. The DS2482 cannot distinguish between a short and a DS1994 or DS2404 signaling a 1-Wire interrupt. For this reason, if a DS2404/DS1994 is used in the application, the interrupt function must be disabled. The interrupt signaling is explained in the respective device data sheets. Logic Level (LL) The LL bit reports the logic state of the active 1-Wire line without initiating any 1-Wire communication. The 1-Wire line is sampled for this purpose every time the Status Register is read. The sampling and updating of the LL bit takes place when the host processor has addressed the DS2482 in read mode (during the acknowledge cycle), provided that the Read Pointer is positioned at the Status Register. Device Reset (RST) If the RST bit is 1, the DS2482 has performed an internal reset cycle, either caused by a power-on reset or from executing the Device Reset command. The RST bit is cleared automatically when the DS2482 executes a Write Configuration command to restore the selection of the desired 1-Wire features. 8 of 23 DS2482-800: Eight-Channel 1-Wire Master Single Bit Result (SBR) The SBR bit reports the logic state of the active 1-Wire line sampled at tMSR of a 1-Wire Single Bit command or the first bit of a 1-Wire Triplet command. The power-on default of SBR is 0. If the 1-Wire Single Bit command sends a 0-bit, SBR should be 0. With a 1-Wire Triplet command, SBR could be 0 as well as 1, depending on the response of the 1-Wire devices connected. The same result applies to a 1-Wire Single Bit command that sends a 1-bit. Triplet Second Bit (TSB) The TSB bit reports the logic state of the active 1-Wire line sampled at tMSR of the second bit of a 1-Wire Triplet command. The power-on default of TSB is 0. This bit is updated only with a 1-Wire Triplet command and has no function with other commands. Branch Direction Taken (DIR) Whenever a 1-Write Triplet command is executed, this bit reports to the host processor the search direction that was chosen by the 3rd bit of the triplet. The power-on default of DIR is 0. This bit is updated only with a 1-Wire Triplet command and has no function with other commands. For additional information see the description of the 1Wire Triplet command and the Dallas Application Note 187, "1-Wire Search Algorithm". FUNCTION COMMANDS The DS2482 understands 9 function commands, which fall into four categories: device control, IC communication, 1-Wire setup and 1-Wire communication. The feedback path to the host is controlled by a read pointer, which is set automatically by each function command for the host to efficiently access relevant information. The host processor sends these commands and applicable parameters as strings of one or two bytes using the IC interface. The IC protocol requires that each byte be acknowledged by the receiving party to confirm acceptance or not be acknowledged to indicate an error condition (invalid code or parameter) or to end the communication. Details of the IC protocol including acknowledge are found in the IC interface description of this document. Device Reset Command Code Command Parameter Description Typical Use Restriction Error Response Command Duration 1-Wire Activity Read Pointer Position Status Bits Affected Configuration Bits Affected F0h None Performs a global reset of device state machine logic, which in turn selects IO0 as the active 1-Wire channel. Terminates any ongoing 1-Wire communication. Device initialization after power-up; re-initialization (reset) as desired. None (can be executed at any time) None Maximum 525ns, counted from falling SCL edge of the command code acknowledge bit. Ends maximum 262.5ns after the falling SCL edge of the command code acknowledge bit. Status Register (for busy polling) RST set to 1, 1WB, PPD, SD, SBR, TSB, DIR set to 0 1WS, APU, SPU set to 0 9 of 23 DS2482-800: Eight-Channel 1-Wire Master Set Read Pointer Command Code Command Parameter Description Typical Use Restriction Error Response Command Duration 1-Wire Activity Read Pointer Position Status Bits Affected Configuration Bits Affected Valid Pointer Codes Register Selection Status Register Read Data Register Channel Selection Register Configuration Register Code F0h E1h D2h C3h E1h Pointer Code Sets the read pointer to the specified register. Overwrites the read pointer position of any 1-Wire communication command in progress. To prepare reading the result from a 1-Wire Byte command; random read access of registers. None (can be executed at any time) If the pointer code is not valid, the pointer code will not be acknowledged and the command will be ignored. None; the read pointer is updated on the rising SCL edge of the pointer code acknowledge bit. Not Affected As Specified by the Pointer Code None None Write Configuration Command Code Command Parameter Description Typical Use Restriction Error Response Command Duration 1-Wire Activity Read Pointer Position Status Bits Affected Configuration Bits Affected D2h Configuration Byte Writes a new configuration byte. The new settings take effect immediately. NOTE: When writing to the Configuration Register, the new data is accepted only if the upper nibble (bits 7 to 4) is the one's complement of the lower nibble (bits 3 to 0). When read, the upper nibble is always 0h. Defining the features for subsequent 1-Wire communication. 1-Wire activity must have ended before the DS2482 can process this command. Command code and parameter will not be acknowledged if 1WB = 1 at the time the command code is received and the command will be ignored. None; the configuration register is updated on the rising SCL edge of the configuration byte acknowledge bit. None Configuration Register (to verify write) RST set to 0 1WS, SPU, APU updated 10 of 23 DS2482-800: Eight-Channel 1-Wire Master Channel Select Command Code Command Parameter Description Typical Use Restriction Error Response Command Duration 1-Wire Activity Read Pointer Position Status Bits Affected Configuration Bits Affected Valid Channel Selection Codes Channel Selection Channel IO0 (default) Channel IO1 Channel IO2 Channel IO3 Channel IO4 Channel IO5 Channel IO6 Channel IO7 Code (to be written) F0h E1h D2h C3h B4h A5h 96h 87h Code (read back) B8h B1h AAh A3h 9Ch 95h 8Eh 87h C3h Selection Code Sets the 1-Wire IO channel for subsequent 1-Wire communication commands. NOTE: The selection code read back is different from the code written. See the table below for the respective values. Selecting a 1-Wire IO channel other that IO0; randomly selecting one of the available 1-Wire IO channels. 1-Wire activity must have ended before the DS2482 can process this command. Command code and parameter will not be acknowledged if 1WB = 1 at the time the command code is received and the command will be ignored. If the selection code is not valid, the selection code will not be acknowledged and the command will be ignored. None; the channel selection register is updated on the rising SCL edge of the selection code acknowledge bit. None Channel Selection Register (to verify write) None None Figure 4. 1-Wire Reset/Presence Detect Cycle RESET PULSE PRESENCE/SHORT DETECT PRESENCE PULSE VCC VIH1 VIL1 0V tF1 APU CONTROLLED EDGE tSI tMSP tRSTL Pullup DS2482 Pulldown tRSTH RESISTIVE PULLUP 1-W Slave Pulldown 11 of 23 DS2482-800: Eight-Channel 1-Wire Master 1-Wire Reset Command Code Command Parameter Description Typical Use Restriction Error Response Command Duration 1-Wire Activity Read Pointer Position Status Bits Affected Configuration Bits Affected B4h None Generates a 1-Wire Reset/Presence Detect cycle (Figure 4) at the selected IO channel. The state of the 1-Wire line is sampled at tSI and tMSP and the result is reported to the host processor through the status register, bits PPD and SD. To initiate or end any 1-Wire communication sequence. 1-Wire activity must have ended before the DS2482 can process this command. Command code will not be acknowledged if 1WB = 1 at the time the command code is received and the command will be ignored. tRSTL + tRSTH + maximum 262.5ns, counted from the falling SCL edge of the command code acknowledge bit. Begins maximum 262.5ns after the falling SCL edge of the command code acknowledge bit. Status Register (for busy polling) 1WB (set to 1 for tRSTL + tRSTH), PPD is updated at tRSTL + tMSP, SD is updated at tRSTL + tSI 1WS, APU apply 1-Wire Single Bit Command Code Command Parameter Description 87h Bit Byte Generates a single 1-Wire time slot with a bit value `V' as specified by the bit byte at the selected 1-Wire IO channel. A `V' value of 0b will generate a write-zero time slot (Figure 5), a value of 1b will generate a write one slot, which also functions as a read data time slot (Figure 6). In either case the logic level at the 1-Wire line is tested at tMSR and SBR is updated. To perform single bit writes or reads on a 1-Wire IO channel when single bit communication is necessary (the exception). 1-Wire activity must have ended before the DS2482 can process this command. Command code and bit byte will not be acknowledged if 1WB = 1 at the time the command code is received and the command will be ignored. tSLOT + maximum 262.5ns, counted from the falling SCL edge of the first bit (MS bit) of the bit byte. Begins maximum 262.5ns after the falling SCL edge of the MS bit of the bit byte. Status Register (for busy polling and data reading) 1WB (set to 1 for tSLOT) SBR is updated at tMSR DIR (may change its state) 1WS, APU, SPU apply Typical Use Restriction Error Response Command Duration 1-Wire Activity Read Pointer Position Status Bits Affected Configuration Bits Affected Bit Allocation in the Bit Byte bit 7 bit 6 bit 5 bit 4 V x x x x = don't care bit 3 x bit 2 x bit 1 x bit 0 x 12 of 23 DS2482-800: Eight-Channel 1-Wire Master Figure 5. Write-0 Time Slot Vcc VIH1 VIL1 0V tREC0 tMSR tW0L tF1 Pullup (see Fig. 2) tSLOT DS2482 Pulldown Figure 6. Write-1 and Read-Data Time Slot Vcc VIH1 VIL1 0V tF1 tSLOT Pullup (see Fig. 2) DS2482 Pulldown 1-W Slave Pulldown tW1L tMSR NOTE on Figure 7: Depending on its internal state, a 1-Wire slave device will transmit data to its master (e.g., the DS2482). When responding with a 0, a 1-Wire slave will start pulling the line low during tW1L; its internal timing generator determines when this pulldown ends and the voltage starts rising again. When responding with a 1, a 1Wire slave will not hold the line low at all, and the voltage starts rising as soon as tW1L is over. 1-Wire device data sheets use the term tRL instead of tW1L to describe a read-data time slot. Technically, tRL and tW1L have identical specifications and cannot be distinguished from each other. 1-Wire Write Byte Command Code Command Parameter Description Typical Use Restriction Error Response Command Duration A5h Data Byte Writes single data byte to selected 1-Wire IO channel. To write commands or data to a 1-Wire IO channel; equivalent to executing eight 1-Wire Single Bit commands, but faster due to less IC traffic. 1-Wire activity must have ended before the DS2482 can process this command. Command code and data byte will not be acknowledged if 1WB = 1 at the time the command code is received and the command will be ignored. 8 x tSLOT + maximum 262.5ns, counted from falling edge of the last bit (LS bit) of the data byte. Begins maximum 262.5ns after falling SCL edge of the LS bit of the data byte (i.e., before the data byte acknowledge). NOTE: The bit order on the IC bus and the 1-Wire line is different. (1-Wire: LS-bit first; IC: MS-bit first) Therefore, 1-Wire activity cannot begin before the DS2482 has received the full data byte. Status Register (for busy polling) 1WB (set to 1 for 8 x tSLOT) 1WS, SPU, APU apply 13 of 23 1-Wire Activity Read Pointer Position Status Bits Affected Configuration Bits Affected DS2482-800: Eight-Channel 1-Wire Master 1-Wire Read Byte Command Code Command Parameter Description Typical Use Restriction Error Response Command Duration 1-Wire Activity Read Pointer Position Status Bits Affected Configuration Bits Affected 96h None Generates eight read data time slots on the selected 1-Wire IO channel and stores result in the Read Data Register. To read data from a 1-Wire IO channel; equivalent to executing eight 1Wire Single Bit commands with V = 1 (write 1 time slot), but faster due to less IC traffic. 1-Wire activity must have ended before the DS2482 can process this command. Command code will not be acknowledged if 1WB = 1 at the time the command code is received and the command will be ignored. 8 x tSLOT + maximum 262.5ns, counted from the falling SCL edge of the command code acknowledge bit. Begins maximum 262.5ns after the falling SCL edge of the command code acknowledge bit. Status Register (for busy polling) NOTE: To read the data byte received from the 1-Wire IO channel, issue the Set Read Pointer command and select the Read Data Register. Then access the DS2482 in read mode. 1WB (set to 1 for 8 x tSLOT) 1WS, APU apply 1-Wire Triplet Command Code Command Parameter 78h Direction Byte Generates three times slots, two read-time slots and one-write time slot, at the selected 1-Wire IO channel. The type of write-time slot depends on the result of the read-time slots and the direction byte. The direction byte determines the type of write-time slot if both read-time slots are 0 (a typical case). In this case the DS2482 will generate a write-1 time slot if V = 1 and a write-0 time slot if V = 0. If the read-time slots are 0 and 1, there will follow a write 0 time slot. If the read-time slots are 1 and 0, there will follow a write 1 time slot. If the read-time slots are both 1 (error case), the subsequent write time slot will be a write 1. To perform a 1-Wire Search ROM sequence; a full sequence requires this command to be executed 64 times to identify and address one device. 1-Wire activity must have ended before the DS2482 can process this command. Command code and direction byte will not be acknowledged if 1WB = 1 at the time the command code is received and the command will be ignored. 3 x tSLOT + maximum 262.5ns, counted from the falling SCL edge of the first bit (MS bit) of the direction byte. Begins maximum 262.5ns after the falling SCL edge of the MS bit of the direction byte. Status Register (for busy polling) 1WB (set to 1 for 3 x tSLOT) SBR is updated at the first tMSR TSB and DIR are updated at the second tMSR (i.e., at tSLOT + tMSR) 1WS, APU apply Description Typical Use Restriction Error Response Command Duration 1-Wire Activity Read Pointer Position Status Bits Affected Configuration Bits Affected 14 of 23 DS2482-800: Eight-Channel 1-Wire Master Bit Allocation in the Direction Byte bit 7 bit 6 bit 5 bit 4 bit 3 V x x x x x = don't care bit 2 x bit 1 x bit 0 x IC INTERFACE General Characteristics The IC bus uses a data line (SDA) plus a clock signal (SCL) for communication. Both SDA and SCL are bidirectional lines, connected to a positive supply voltage through a pullup resistor. When there is no communication, both lines are HIGH. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. Data on the IC bus can be transferred at rates of up to 100kbps in the Standard-mode, up to 400kbps in the Fast-mode. The DS2482 works in both modes. A device that sends data on the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls the communication is called a "master." The devices that are controlled by the master are "slaves." To be individually accessed, each device must have a slave address that does not conflict with other devices on the bus. Data transfers may be initiated only when the bus is not busy. The master generates the serial clock (SCL), controls the bus access, generates the START and STOP conditions, and determines the number of data bytes transferred between START and STOP (Figure 7). Data is transferred in bytes with the most significant bit being transmitted first. After each byte follows an acknowledge bit to allow synchronization between master and slave. Figure 7. IC Protocol Overview MS-bit SDA Slave Address Acknowledgment from Receiver Repeated if more bytes are transferred R/W ACK bit ACK bit SCL Idle START Condition 1 2 6 7 8 9 ACK 1 2 8 9 ACK STOP Condition Repeated START Condition Slave Address The slave address to which the DS2482 responds is shown in Figure 8. The logic states at the address pins AD0, AD1 and AD2 determine the value of the address bits A0, A1, and A2. The address pins allow the device to respond to one of eight possible slave addresses. The slave address is part of the slave-address/control byte. The last bit of the slave-address/control byte (R/W) defines the data direction. When set to a 0, subsequent data will flow from master to slave (write access); when set to a 1, data will flow from slave to master (read access). 15 of 23 DS2482-800: Eight-Channel 1-Wire Master Figure 8. DS2482 Slave Address 7-Bit Slave Address A6 0 A5 0 A4 1 A3 1 A2 A1 A0 AD2 AD1 AD0 R/W Most Significant Bit AD2, AD1, AD0 Pin States Determines Read or Write IC Definitions The following terminology is commonly used to describe IC data transfers. The timing references are defined in Figure 9. Bus Idle or Not Busy: Both, SDA and SCL, are inactive and in their logic HIGH states. START Condition: To initiate communication with a slave, the master has to generate a START condition. A START condition is defined as a change in state of SDA from HIGH to LOW while SCL remains HIGH. STOP Condition: To end communication with a slave, the master has to generate a STOP condition. A STOP condition is defined as a change in state of SDA from LOW to HIGH while SCL remains HIGH. Repeated START Condition: Repeated starts are commonly used for read accesses to select a specific data source or address to read from. The master can use a repeated START condition at the end of a data transfer to immediately initiate a new data transfer following the current one. A repeated START condition is generated the same way as a normal START condition, but without leaving the bus idle after a STOP condition. Data Valid: With the exception of the START and STOP condition, transitions of SDA may occur only during the LOW state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the required setup and hold time (tHD:DAT after the falling edge of SCL and tSU:DAT before the rising edge of SCL, see Figure 9). There is one clock pulse per bit of data. Data is shifted into the receiving device during the rising edge of the SCL. When finished with writing, the master must release the SDA line for a sufficient amount of setup time (minimum tSU:DAT + tR in Figure 9) before the next rising edge of SCL to start reading. The slave shifts out each data bit on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. The master generates all SCL clock pulses, including those needed to read from a slave. Acknowledge: Usually, a receiving device, when addressed, is obliged to generate an acknowledge after the receipt of each byte. The master must generate a clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull SDA LOW during the acknowledge clock pulse in such a way that SDA is stable LOW during the HIGH period of the acknowledge-related clock pulse plus the required setup and hold time (tHD:DAT after the falling edge of SCL and tSU:DAT before the rising edge of SCL). Not Acknowledged by Slave: A slave device may be unable to receive or transmit data, e.g., because it is busy performing some real-time function. In this case the slave device will not acknowledge its slave address and leave the SDA line HIGH. A slave device that is ready to communicate will acknowledge at least its slave address. However, some time later the slave may refuse to accept data, e.g., because of an invalid command code or parameter. In this case the slave device will not acknowledge any of the bytes that it refuses and will leave SDA HIGH. In either case, after a slave has failed to acknowledge, the master first needs to generate a repeated START condition or a STOP condition followed by a START condition to begin a new data transfer. 16 of 23 DS2482-800: Eight-Channel 1-Wire Master Not Acknowledged by Master: At some time when receiving data, the master must signal an end of data to the slave device. To achieve this, the master does not acknowledge the last byte that it has received from the slave. In response, the slave releases SDA, allowing the master to generate the STOP condition. Figure 9. IC Timing Diagram SDA tBUF tLOW tF tHD:STA tSP SCL tHD:STA tR tHD:DAT STOP START tHIGH tSU:DAT Repeated START tSU:STA Spike Suppression tSU:STO NOTE: Timing is referenced to VILMAX and VIHMIN. Writing to the DS2482 To write to the DS2482, the master must access the device in write mode, i.e., the slave address must be sent with the direction bit set to 0. The next byte to be sent is a command code, which, depending on the command, may be followed by a command parameter. The DS2482 will acknowledge valid command codes and expected/valid command parameters. Additional bytes or invalid command parameters will never be acknowledged. Reading from the DS2482 To read from the DS2482, the master must access the device in read mode, i. e., the slave address must be sent with the direction bit set to 1. The read pointer determines the register that the master will read from. The master may continue reading the same register over and over again, without having to re-address the device, e. g., to watch the 1WB changing from 1 to 0. To read from a different register, the master must issue the Set Read Pointer command and then access the DS2482 again in read mode. IC Communication--Legend SYMBOL S AD,0 AD,1 Sr P A A\ (Idle) 17 of 23 DS2482-800: Eight-Channel 1-Wire Master Data Direction Codes Master-to-Slave Slave-to-Master IC Communication Examples Device Reset, e.g., after power-up S AD,0 A DRST A Sr AD,1 A A\ P The master should stop and restart as soon as the DS2482 does not acknowledge the command code. Channel Select, e.g., to select another 1-Wire channel Case A: 1-Wire idle (1WB = 0) S AD,0 A CHSL A E1h A Sr AD,1 A A E5h A\ P 18 of 23 DS2482-800: Eight-Channel 1-Wire Master 1-Wire Reset, e.g., to begin or end 1-Wire communication Case A: 1-Wire idle (1WB = 0), no busy polling to read the result S AD,0 A 1WRS A P (Idle) S AD,1 A Repeat until the 1WB bit has changed to 0 Case C: 1-Wire busy (1WB = 1) S AD,0 A 1WRS A\ P The master should stop and restart as soon as the DS2482 does not acknowledge the command code. 1-Wire Write Byte, e.g., to send a command code to a 1-Wire IO channel Case A: 1-Wire idle (1WB = 0), no busy polling S AD,0 A 1WWB A 33h A P (Idle) 33h is the valid 1-Wire ROM function command for Read ROM. The idle time is needed for the 1-Wire function to complete. There is no data read back from the 1-Wire line with this command. Case B: 1-Wire idle (1WB = 0), busy polling until the 1-Wire Command is completed. S AD,0 A 1WWB A 33h A Repeat until the 1WB bit has changed to 0 A\ P Sr AD,1 A Case C: 1-Wire busy (1WB = 1) S AD,0 A 1WWB A\ P The master should stop and restart as soon as the DS2482 does not acknowledge the command code. 1-Wire Read Byte, e. g., to read a byte from a 1-Wire IO channel Case A: 1-Wire idle (1WB = 0), no busy polling, set read pointer after idle time. S AD,0 A 1WRB A P (Idle) S AD,0 A SRP A E1h A Sr AD,1 A The idle time is needed for the 1-Wire function to complete. Then set the read pointer to the read data register (code E1h) and access the device again to read the data byte that was obtained from the 1-Wire IO channel. Case B: 1-Wire idle (1WB = 0), no busy polling, set read pointer before idle time. S AD,0 A 1WRB A Sr AD,0 A SRP A (Idle) S AD,1 A E1h P A P The read pointer is set to the read data register (code E1h) while the 1-Wire Read Byte command is still in progress. Then, after the 1-Wire function is completed, the device is accessed to read the data byte that was obtained from the 1-Wire IO channel. 19 of 23 DS2482-800: Eight-Channel 1-Wire Master Case C: 1-Wire idle (1WB = 0), busy polling until the 1-Wire Command is completed. Repeat until the 1WB S AD,0 A 1WRB A bit has changed to 0 Sr AD,1 A Sr AD,0 A SRP A E1h A Sr AD,1 A A\ P The master should stop and restart as soon as the DS2482 does not acknowledge the command code. 1-Wire Single Bit, e. g., to generate a single time slot on a 1-Wire IO channel Case A: 1-Wire idle (1WB = 0), no busy polling S AD,0 A 1WSB A S AD,1 A Sr AD,1 A S AD,1 A 20 of 23 DS2482-800: Eight-Channel 1-Wire Master Case C: 1-Wire busy (1WB = 1) S AD,0 A 1WT A\ P The master should stop and restart as soon as the DS2482 does not acknowledge the command code. Figure 10. Application Schematic Application Information SDA and SCL Pullup Resistors SDA is an open-drain output on the DS2482 that requires a pullup resistor to realize high logic levels. Because the DS2482 uses SCL only as input (no clock stretching) the master can drive SCL either through an opendrain/collector output with a pullup resistor or a push-pull output. Pullup Resistor RP Sizing According to the IC specification, a slave device must be able to sink at least 3mA at a VOL of 0.4V. This DC condition determines the minimum value of the pullup resistor: Rpmin = (VCC - 0.4V)/3mA. With an operating voltage of 5.5V, the minimum value for the pullup resistor is 1.7k. The "Minimum RP" line in Figure 11 shows how the minimum pullup resistor changes with the operating voltage. For IC systems, the rise time and fall time are measured from 30% to 70% of the pullup voltage. The maximum bus capacitance CB is 400pF. The maximum rise time at standard speed must not exceed 1000ns and 300ns at fast speed. Assuming maximum rise time, the maximum resistor value at any given capacitance Cb is calculated as: Rpmaxs = 1000ns/(CB*ln(7/3)) (standard speed) and Rpmaxf = 300ns/(CB*ln(7/3)) (fast speed). For a bus capacitance of 400pF the maximum pullup resistor values are 2.95k at standard speed and 885 at fast speed. A value between of 1.7k and 2.95k meets all requirements at standard speed. Since a 885 pullup resistor, as would be required to meet the rise time specification at fast speed and 400pF bus capacitance, is lower than Rpmin at 5.5V, a different approach is necessary. The "Max. Load..." line in Figure 11 is generated by first calculating the minimum pullup resistor at any given operating voltage ("Minimum Rp" line) and then calculating the respective bus capacitance that yields a rise time of 300ns. 21 of 23 DS2482-800: Eight-Channel 1-Wire Master Only for pullup voltages of 3V and lower can the maximum permissible bus capacitance of 400pF be maintained. A reduced bus capacitance of 300pF is acceptable for pullup voltages of 4V and lower. For fast speed operation at any pullup voltage, the bus capacitance must not exceed 200pF. The corresponding pullup resistor value at the voltage is indicated by the "Minimum Rp" line. Figure 11. IC Fast Mode Pullup Resistor Selection Chart "Minimum Rp" 2000 Minimum Rp (Ohms) 1600 1200 800 400 0 1 2 3 Pull-up Voltage 4 5 Max. Load at Min. Rp fast mode 500 400 300 200 100 0 Load (pF) PACKAGE INFORMATION For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 16 SO (150 mil) S16+5 21-0041 22 of 23 DS2482-800: Eight-Channel 1-Wire Master REVISION HISTORY REVISION DATE 8/08 DESCRIPTION Removed the 1-Wire line termination resistor and references to it from the Typical Operating Circuit and Figure 11. Conversion to lead (Pb) free product. Removed the presence pulse masking feature. Revised the recommendation on the use of active pullup. PAGES CHANGED 1, 21 1 1, 3, 4, 5, 6, 7, 9, 10, 11, 12 6 11/09 23 of 23 |
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